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Sr FPGA Design Engineer

Company: Modis
Location: Warren
Posted on: November 22, 2021

Job Description:

An FPGA Design Engineer position in Warren, NJ is open courtesy of Modis Engineering. - - Duration: - 1 year with possibility of extension and conversion to direct hire employment with client. Rat: - $75.00 - $85.00/hour Job Description:

  • 10+ years of RTL design experience (including synthesis, timing analysis, etc.)
  • Experience with Vivado and Xilinx Ultrascale+ devices (RFSoC is a plus)
  • Proficiency in Verilog/SystemVerilog
  • Some DSP background in Wireless Comm
  • Linux experience - If you are interested in this FPGA Design E/ngineer -job -in Janesville, WI then please click APPLY NOW. - For other opportunities available at Modis Engineering go to -. - - - If you have questions about the position, please contact Mike Leeson at (253)347-9305 or email - . Equal Opportunity Employer/Veterans/DisabledTo read our Candidate Privacy Information Statement, which explains how we will use your information, please navigate to https://www.modis.com/en-us/candidate-privacyThe Company will consider qualified applicants with arrest and conviction records

Keywords: Modis, Elizabeth , Sr FPGA Design Engineer, Engineering , Warren, New Jersey

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